1. Field of the Invention
The present invention relates to a synchronous semiconductor memory which performs a pipeline operation and, more particularly, to a semiconductor memory in which error correction is performed by an on-chip error correction circuit.
2. Description of the Related Art
A synchronous semiconductor memory which operates in synchronism with an externally input clock signal in order to perform high-speed data transfer is known. Also, to improve the reliability, an on-chip error correcting technique using an error correction circuit is used (e.g., IEEE Spectrum April 2000, “Adding error-correcting circuitry to ASIC memory”, Gray, K.; Spectrum, IEEE Volume 37, Issue 4, April. 2000, Pages: 55-60, Digital Object Identifier 10.1109/6.833029). This synchronous semiconductor memory having an error correcting function performs data write and read as follows.
In a write operation to a memory cell, 128 input information bits, for example, are directly written in the memory cell in the case of a systematic code, i.e., a code in which the same bits as information bits are contained in a code word. In addition, an 8-bit parity (also called check bits or code bits in some cases) is generated from the 128 information bits and written in a memory cell for parity bits.
In a read operation, the 128 information bits and 8 parity bits are read out from the memory cells to generate a syndrome. One information bit error can be corrected by decoding the generated syndrome.
It is sometimes necessary to write data having less than 128 bits by using a write mask function when the internal bus width is, e.g., 128 bits. Since, however, the write data has less than 128 bits, no correct code can be directly generated. Therefore, data must be read out once from a memory cell at the write address. This requires a so-called “read modify write” operation including read from the memory cell, error correction, overwrite of the write data, code generation, and write to the memory cell.
Accordingly, the data transfer rate decreases when the length of externally input write data is smaller than the internal bus width. This operation can occur not only when the write mask function is used, but also when the external bus width is smaller than the internal bus width.